Toshiba selects Cadence Image Recognition Processor for its ADAS Chip

Toshiba has implemented the Cadence Tensilica Vision P6 DSPs for its next-generation automotive SoC to meet functional safety requirements.

The Vision P6 DSP claims to provide high compute throughput with low power consumption, small core area and a strong partner ecosystem, and is certified to meet functional safety requirements, making it the ideal choice for automotive applications.

According to Toshiba Cadence Tensilica Vision P6 DSP provides performance at par as the image recognition processor in its next-generation ADAS chip. This DSP enabled the company to execute complex algorithms for accurate detection and identification of a wide range of objects while consuming very low power, which is crucial for today’s automotive applications.

By leveraging the optimized instruction set of the Vision P6 DSP, Toshiba can execute several driver-assistance functions simultaneously on one chip and in real time

Source: Press Release


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