MEMTECH introduces new LPDDR5X automotive memory controller

MEMTECH‘s LPDDR5X Memory Controller is hardware-evaluated to meet the Automotive Safety Integrity Level (ASIL). The solution is part of MEMTECH’s new portfolio of memory interface solution targeted for automotive functional safety based on International Organization for Standardization (ISO) 26262 standard. In addition to these, LPDDR5X Memory Controller comes with an optional functional safety package including FMEA (Failure Mode and Effect Analysis).

MEMTECH’s functional safety-evaluated LPDDR5X memory controller is compatible with advanced-driver assistance system (ADAS) technologies, including adaptive cruise control, automatic emergency braking systems, lane departure warning and blind spot detection systems. MEMTECH’s LPDDR5X memory controller’s high-performance, superior power efficiency and low latency provide the needed performance to keep pace with increasing demand of high-bandwidth of next generation automotive systems.

MEMTECH’s low-power memory interface controller for automotive drives a greener transportation

As the adoption of ADAS and other autonomous technologies become mainstream, data capture, storage, and higher bandwidth become key for innovation. MEMTECH’s LPDDR5X Controller addresses these challenges with increased in data access speeds and significant improvement in power efficiency, enabling fast decision making from a plethora of data sources including sensors, radar, lidar, hi-resolution imaging, 5G networking and image recognition. Support for LPDDR5X memories minimizes power consumption for both electric as well as conventional vehicles for a greener transportation.

Safety is paramount

Accompanied by extensive functional safety assurance, MEMTECH’s LPDDR5X memory controller supports customers in conducting safety analysis during various system configurations. The hardware evaluation report verifies extensive safety analysis in strictest compliance with ISO 26262. LPDDR5X memory controller incorporates safety mechanisms to detect and control memory errors during operations, as well as provisions that can be implemented by system integrators to reduce risks.

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